The Communication Performance of Link-Sharing Method of Buffer in NoC Router
DOI:
https://doi.org/10.14738/tnc.11.20Abstract
We have proposed a memory sharing method of the wormhole routed network-on-chip architecture. In our method, a memory is shared between multiple physical links by using the multi-port memory. In this paper, we present the pipeline processing method, and evaluate the communication performance in the various situations. The pipeline of the proposed method has two courses of the route 1 and 2. The number of pipeline stages of route2 is 2 stages larger than the traditional router in order to use a shared memory. But delay is concealed if the capacity of a private buffer is enough. It is shown that the required number of memory banks required in multiport memory for 2-dimensional torus and 2-dimensional mesh networks is 8. Our proposed method yields high performance for both torus and mesh networks. Even this high performance is retained when the buffer size and the packet length are same.
References
Kumary, P.Kunduz, A.P.Singhx, L.-S.Pehy, N.K.Jhay, A 4.6its/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS, 25th International Conference on Computer Design(ICCD 2007), pp.63-70, 2007.
Gregory L. Frazier, Yuval Tamir, The design and implementation of a multiqueue buffer for VLSI communication switches, Proceedings of the International Conference on Computer Design Cambridge, Massachusetts, pp.466-471, 1989.
Yuval Tamir, Gregory L. Frazier, Dynamically-Allocated Multi-Queue Buffers for VLSI Communication Switches, IEEE Trans. Computers, Vol.41, No.6, pp.725-737, 1992.
A. Ahmadinia and A. Shahrabi, A Highly Adaptive and Efficient Router Architecture for Network-on- Chip, The Computer Journal, Vol.54 Issue 8, pp.1295-1307, 2011.
R.S. Ramanujam, V. Soteriou, B. Lin and L.S. Peh, Extending the Effective Throughput of NoCs with Distributed Shared-Buffer Routers, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, vol.30, No.4, pp.548-561, 2011.
Naohisa Fukase,Yasuyuki Miura,Shigeyoshi Watanabe,Link-Sharing Method of Buffer in Direct-Connection Network,The 2011 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, pp.208-213, 2011.
Naohisa Fukase, Yasuyuki Miura, Shigeyosi Watanabe, The Hardware Cost Reduction Method of Control Circuit for Link-Sharing Method of Buffer in NoC Router, 2013 RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing, March 2013.
Naohisa Fukase, Yasuyuki Miura, Shigeyosi Watanabe, The Proposal of Link-Sharing Method of Buffer in NoC Router : Implementation and Communication Performance, Jounal of Basic and Applied Physics, (In printing).
Michael Golden et al., “A 500MHz write-bypassed, 88-entry, 90bit register file,” Proc. of Symposium on VLSI Technology, Session C11-1, 1999.
H.J Mattausch, K.Kishi and T.Gyohten, “Area-efficient multi-port SRAMs for on-chip data-storage withhigh random-access bandwidth and large storage capacity,” IEICE Trans. Electron., Vol.E84-C, No.3, p410, 2001.
W.J.Dally, Virtual-Channel Flow Control, IEEE Trans on Parallel and Destributed Systems, Vol. 3, No. 2, 1992.
M. Ni and P. K. McKinley, A Survey of Wormhole Routing Techniques in Direct Networks, Proc of the IEEE, Vol. 81, No. 2, pp. 62-76, 1993.
E. Fleury and P.Fraigniaud, A General Theory for Deadlock Avoidance in Wormhole-Routing Networks, IEEE Trans. Parallel and Distributed Systems, Vol. 9, No. 7, pp. 626-638, 1998.