Performance Evaluation of Low Density Parity Check (LDPC) Codes Over Gigabit Ethernet Protocol
DOI:
https://doi.org/10.14738/tnc.45.2035Keywords:
LDPC, BER, PER, FPGA, Gigabit EthernetAbstract
Error Correcting Low density Parity Check codes enable the communication systems to have a low-power, reliable transmission over noisy channels and can achieve data rates very close to Shannon limit when iteratively decoded. They are used in many digital communication systems such as digital video broadcasting (DVB-S2), MIMO-WLAN (802.11n), WMAN (802.16e), mobile broadband wireless access (MBW A) (802.20) and have a very good error correcting performance over a variety of channels. In this paper we present a performance platform for simulation studies of of LDPC decoding algorithms. We present the results of the simulation studies of Bit Error Rate (BER) performance for various block length like 64 and 256 bytes frame over Additive White Gaussian Noise (AWGN) channel. The comparative studies are made for Log Domain and Log Doman Simple decoding algorithms.
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